16位RISC硬布线模型机设计与实现
指令集设计
指令格式采用12位操作码、2位目的寄存器(RD)和2位源寄存器(RS)的固定编码方案，共计8条指令：
| 助记符 | OP码(12位) | RD | RS | 功能描述 |
|---|---|---|---|---|
| IN | 001H | RD | XX | 从键盘读取数据存入RD |
| SUB | 002H | RD | RS | RD - RS → RD |
| STA | 003H | RD | RS | RS → [RD] |
| LD | 004H | RD | RS | [RS] → RD |
| MOV | 005H | RD | RS | RS → RD |
| ADD | 006H | RD | RS | RS + RD → RD |
| OUT | 007H | XX | RS | RS → 总线输出 |
| JMP | 008H | XX | RS | RS → PC |
测试程序示例
| 地址(Hex) | 机器码(Hex) | 汇编指令 | 执行说明 |
|---|---|---|---|
| 00 | 0013 | IN R0 | R0 = 0x04 |
| 01 | 0017 | IN R1 | R1 = 0x01 |
| 02 | 0021 | SUB R0, R1 | R0 = 0x04 - 0x01 = 0x03 |
| 03 | 007C | OUT R0 | 总线输出R0 |
| 04 | 001B | IN R2 | R2 = 0xFF |
| 05 | 0038 | STA R2, R0 | R0 → [R2] |
| 06 | 0046 | LD R1, R2 | [R2] → R1, R1 = 0x03 |
| 07 | 007D | OUT R1 | 总线输出R1 |
| 08 | 0051 | MOV R0, R1 | R0 = R1 = 0x03 |
| 09 | 0061 | ADD R0, R1 | R0 = 0x03 + 0x03 = 0x06 |
| 0A | 007C | OUT R0 | 总线输出R0 |
| 0B | 0013 | IN R0 | R0 = 0 |
| 0C | 008C | JMP R0 | 跳转到地址00 |
硬布线控制器设计
指令执行流程图
每条指令的执行划分为两个机器周期M1和M2，每个周期内包含4个时序节拍T1-T4。M1周期负责取指令操作，M2周期执行具体指令操作。
（流程图图示需保留）
控制信号真值表
控制信号逻辑基于指令类型和当前时序状态确定，其中每格内容表示该控制信号在该指令下有效的时序条件。以IN指令为例，SW_B信号在M2&T1条件下激活，对应逻辑表达式为 (IN & M2 & T1)。
| 控制信号 | IN(0001) | ADD(0010) | STA(0011) | OUT(0100) | JMP(0101) | SUB(0110) | MOV(0111) | LD(1000) |
|---|---|---|---|---|---|---|---|---|
| SW_B | M2&T1 | |||||||
| LD_REG1 | !(M2&T1)|(M2&T1&IR3) | !(M2&T3)|(M2&T3&IR3) | !(M2&T3)|(M2&T3&IR3) | !(M2&T1)|(M2&T1&IR3) | !(M2&T2)|(M2&T2&IR3) | |||
| LD_REG0 | !(M2&T1)|(M2&T1&IR2) | !(M2&T3)|(M2&T3&IR2) | !(M2&T3)|(M2&T3&IR2) | !(M2&T1)|(M2&T1&IR2) | !(M2&T2)|(M2&T2&IR2) | |||
| SEL1 | !(M2&T1)|(M2&T1&IR3)|!(M2&T2)|(M2&T2&IR1) | !(M2&T1)|(M2&T1&IR3)|!(M2&T2)|(M2&T2&IR1) | !(M2&T1)|(M2&T1&IR1) | !(M2&T1)|(M2&T1&IR1) | !(M2&T1)|(M2&T1&IR3)|!(M2&T2)|(M2&T2&IR1) | !(M2&T1)|(M2&T1&IR1) | !(M2&T1)|(M2&T1&IR1) | |
| SEL0 | !(M2&T1)|(M2&T1&IR2)|!(M2&T2)|(M2&T2&IR0) | !(M2&T1)|(M2&T1&IR2)|!(M2&T2)|(M2&T2&IR0) | !(M2&T1)|(M2&T1&IR0) | !(M2&T1)|(M2&T1&IR0) | !(M2&T1)|(M2&T1&IR2)|!(M2&T2)|(M2&T2&IR0) | !(M2&T1)|(M2&T1&IR0) | !(M2&T1)|(M2&T1&IR0) | |
| REG_B | (M2&T1)|(M2&T2) | (M2&T1)|(M2&T2) | M2&T1 | M2&T1 | (M2&T1)|(M2&T2) | M2&T1 | M2&T1 | |
| LD_DR1 | M2&T2 | M2&T2 | ||||||
| LD_DR0 | M2&T1 | M2&T1 | ||||||
| S3 | 0&M2&T3 | 0&M2&T3 | ||||||
| S2 | 0&M2&T3 | 0&M2&T3 | ||||||
| S1 | 1&M2&T3 | 0&M2&T3 | ||||||
| S0 | 0&M2&T3 | 1&M2&T3 | ||||||
| ALU_B | M2&T3 | M2&T3 | ||||||
| LD_AR | M1&T1 | M1&T1 | (M1&T1)|(M2&T1) | M1&T1 | M1&T1 | M1&T1 | M1&T1 | (M1&T1)|(M2&T1) |
| W/R | M2&T2 | |||||||
| RAM_B | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | (M1&T3)|(M2&T2) |
| LD_PC | M2&T1 | |||||||
| INC_PC | M1&T2 | M1&T2 | M1&T2 | M1&T2 | (M1&T2)|(M2&T1) | M1&T2 | M1&T2 | M1&T2 |
| PC_B | M1&T1 | M1&T1 | M1&T1 | M1&T1 | M1&T1 | M1&T1 | M1&T1 | M1&T1 |
| LD_IR | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 | M1&T3 |
硬布线控制器实现(VHDL)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CONTROL_UNIT IS
PORT(
CLR : IN STD_LOGIC;
IR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TICK1 : IN STD_LOGIC;
TICK2 : IN STD_LOGIC;
TICK3 : IN STD_LOGIC;
TICK4 : IN STD_LOGIC;
ALU_CTL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
REG_EN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
REG_BUS, DR1_LD, DR0_LD, CARRY_IN, ALU_M, ALU_OE,
AR_LD, MEM_WR, MEM_OE, PC_LD, PC_INC, PC_OE, IR_LD : OUT STD_LOGIC;
M_STATE: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SW_IN : OUT STD_LOGIC
);
END CONTROL_UNIT;
ARCHITECTURE RTL OF CONTROL_UNIT IS
SIGNAL M1, M2 : STD_LOGIC := '0';
SIGNAL IN_CMD, ADD_CMD, STA_CMD, OUT_CMD, JMP_CMD, SUB_CMD, MOV_CMD, LD_CMD : STD_LOGIC := '0';
BEGIN
-- 机器周期切换(T4下降沿触发)
PRocESS(TICK4)
BEGIN
IF FALLING_EDGE(TICK4) THEN
IF M1 = '1' THEN
M1 <= '0';
M2 <= '1';
ELSE
M1 <= '1';
M2 <= '0';
END IF;
END IF;
END PROCESS;
-- 组合逻辑：控制信号生成
PROCESS(TICK1, TICK2, TICK3, TICK4, M1, M2, CLR, IR)
VARIABLE tmp : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- 默认值
ALU_CTL <= "0000";
REG_EN <= "11";
SEL <= "11";
REG_BUS <= '0'; DR1_LD <= '0'; DR0_LD <= '0';
CARRY_IN <= '0'; ALU_M <= '0'; ALU_OE <= '0';
AR_LD <= '0'; MEM_WR <= '0'; MEM_OE <= '0';
PC_LD <= '0'; PC_INC <= '0'; PC_OE <= '0';
IR_LD <= '0'; SW_IN <= '0';
-- 复位处理
IF CLR = '1' THEN
-- 所有信号置零
NULL;
END IF;
-- 指令译码
IN_CMD <= '0'; ADD_CMD <= '0'; STA_CMD <= '0';
OUT_CMD <= '0'; JMP_CMD <= '0'; SUB_CMD <= '0';
MOV_CMD <= '0'; LD_CMD <= '0';
CASE IR(7 DOWNTO 4) IS
WHEN "0001" => IN_CMD <= '1';
WHEN "0010" => ADD_CMD <= '1';
WHEN "0011" => STA_CMD <= '1';
WHEN "0100" => OUT_CMD <= '1';
WHEN "0101" => JMP_CMD <= '1';
WHEN "0110" => SUB_CMD <= '1';
WHEN "0111" => MOV_CMD <= '1';
WHEN "1000" => LD_CMD <= '1';
WHEN OTHERS => NULL;
END CASE;
-- 控制信号赋值(基于真值表的逻辑简化)
SW_IN <= IN_CMD AND M2 AND TICK1;
REG_EN(1) <= (IN_CMD AND (NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(3)))) OR
(ADD_CMD AND (NOT (M2 AND TICK3) OR (M2 AND TICK3 AND IR(3)))) OR
(SUB_CMD AND (NOT (M2 AND TICK3) OR (M2 AND TICK3 AND IR(3)))) OR
(MOV_CMD AND (NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(3)))) OR
(LD_CMD AND (NOT (M2 AND TICK2) OR (M2 AND TICK2 AND IR(3))));
REG_EN(0) <= (IN_CMD AND (NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(2)))) OR
(ADD_CMD AND (NOT (M2 AND TICK3) OR (M2 AND TICK3 AND IR(2)))) OR
(SUB_CMD AND (NOT (M2 AND TICK3) OR (M2 AND TICK3 AND IR(2)))) OR
(MOV_CMD AND (NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(2)))) OR
(LD_CMD AND (NOT (M2 AND TICK2) OR (M2 AND TICK2 AND IR(2))));
SEL(1) <= (ADD_CMD OR STA_CMD OR SUB_CMD) AND
((NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(3)) OR
NOT (M2 AND TICK2) OR (M2 AND TICK2 AND IR(1)))) OR
(OUT_CMD OR JMP_CMD OR MOV_CMD OR LD_CMD) AND
((NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(1))));
SEL(0) <= (ADD_CMD OR STA_CMD OR SUB_CMD) AND
((NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(2)) OR
NOT (M2 AND TICK2) OR (M2 AND TICK2 AND IR(0)))) OR
(OUT_CMD OR JMP_CMD OR MOV_CMD OR LD_CMD) AND
((NOT (M2 AND TICK1) OR (M2 AND TICK1 AND IR(0))));
REG_BUS <= ((ADD_CMD OR STA_CMD OR SUB_CMD) AND ((M2 AND TICK1) OR (M2 AND TICK2))) OR
((OUT_CMD OR JMP_CMD OR MOV_CMD OR LD_CMD) AND (M2 AND TICK1));
DR1_LD <= (ADD_CMD OR SUB_CMD) AND (M2 AND TICK2);
DR0_LD <= (ADD_CMD OR SUB_CMD) AND (M2 AND TICK1);
ALU_CTL(1) <= ADD_CMD AND (M2 AND TICK3); -- S1
ALU_CTL(0) <= SUB_CMD AND (M2 AND TICK3); -- S0
ALU_OE <= (ADD_CMD OR SUB_CMD) AND (M2 AND TICK3);
AR_LD <= (M1 AND TICK1) OR ((STA_CMD OR LD_CMD) AND (M2 AND TICK1));
MEM_WR <= STA_CMD AND (M2 AND TICK2);
MEM_OE <= (M1 AND TICK3) OR (LD_CMD AND (M2 AND TICK2));
PC_LD <= JMP_CMD AND M2 AND TICK1;
PC_INC <= (M1 AND TICK2) OR (JMP_CMD AND (M2 AND TICK1));
PC_OE <= M1 AND TICK1;
IR_LD <= M1 AND TICK3;
M_STATE <= M2 & M1;
END PROCESS;
END RTL;
优化方向
可将现有两周期方案压缩为单周期执行模式，即一个机器周期完成一条指令。以ADD R0, R1为例：
T1: PC → AR T2: RAM → IR (取指) T3: R0 → DR0, R1 → DR1 (双端口寄存器组并行传输) T4: DR0 + DR1 → R0, PC+1 (执行与PC更新并行)
通过流水线技术和双端口寄存器堆，可显著提升吞吐率。
系统架构
（整机结构图需保留并标注关键数据通路）
